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K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
Document Title
32Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
For Cisco CMOS SRAM
Revision History
Rev .No. Rev. 0.0 Rev. 1.0 Rev. 2.0 History Initial release with Preliminary. Release to Final Data Sheet. 2.1. Add Low Power Version. 2.2. Add data retention charactoristic. Draft Data Aug. 1. 1998 Nov. 2. 1998 Feb. 25. 1999 Remark Preliminary Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Revision 2.0 Feburary 1999
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
32K x 8 Bit High-Speed CMOS Static RAM
FEATURES
* Fast Access Time 10, 12, 15ns(Max.) * Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 2mA(Max.) 0.6mA(Max.) L-ver. Only Operating K6E0808C1E-10 : 80mA(Max.) K6E0808C1E-12 : 80mA(Max.) K6E0808C1E-15 : 80mA(Max.) * Single 5.0V10% Power Supply * TTL Compatible Inputs and Outputs * I/O Compatible with 3.3V Device * Fully Static Operation - No Clock or Refresh required * Three State Outputs * 2V Minimum Data Retention : L-Ver. only * Standard Pin Configuration K6E0808C1E-J : 28-SOJ-300 K6E0808C1E-T : 28-TSOP1-0813. 4F
For Cisco CMOS SRAM
GENERAL DESCRIPTION
The K6E0808C1E is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The K6E0808C1E uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6E0808C1E is packaged in a 300mil 28-pin plastic SOJ or TSOP1 forward.
PIN CONFIGURATION(Top View)
OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2
TSOP1
ORDERING INFORMATION
K6E0808C1E-C10/C12/C15 K6E0808C1E-I10/I12/I15 Commercial Temp. Industrial Temp.
FUNCTIONAL BLOCK DIAGRAM
A14 1 A12 2 28 Vcc 27 WE 26 A13 25 A8 24 A9 23 A11
Clk Gen.
A0 A1 A2 A3 A4 A5 A6 A7 A8
Pre-Charge-Circuit
A7 3 A6 4 A5 5
Row Select
A4 6
Memory Array 512 Rows 64x8 Columns
A3 7 A2 8 A1 9 A0 10 I/O1 11
SOJ
22 OE 21 A10 20 CS 19 I/O8 18 I/O7 17 I/O6 16 I/O5 15 I/O4
I/O1~I/O8
Data Cont. CLK Gen.
I/O Circuit Column Select
I/O2 12 I/O3 13 Vss 14
PIN FUNCTION
A9 A10 A11 A12 A13 A14
Pin Name CS WE OE A0 - A14 WE CS OE I/O1 ~ I/O8 VCC VSS
Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground
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Revision 2.0 Feburary 1999
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC PD TSTG TA TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85
For Cisco CMOS SRAM
Unit V V W C C C
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5** Typ 5.0 0 Max 5.5 0 VCC+0.5*** 0.8 Unit V V V V
* The above parameters are also guaranteed at industrial temperature range. ** VIL(Min) = -2.0(Pulse Width7ns) for I20mA. *** VIH(Max) = VCC+2.0V(Pulse Width7ns) for I20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70C,VCC=5.0V10% unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA IOH1=0.1mA Normal L-Ver 10ns 12ns 15ns Standby Current ISB ISB1 Min -2 -2 2.4 Max 2 2 80 80 80 20 2 0.6 0.4 3.95 V V V mA mA Unit A A mA
Output Low Voltage Level Output High Voltage Level
VOL VOH VOH1**
* The above parameters are also guaranteed at industrial temperature range. ** VCC=5.0V5%, Temp.=25C.
CAPACITANCE*(TA=25C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN Max 8 7 Unit pF pF
* Capacitance is sampled and not 100% tested.
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Revision 2.0 Feburary 1999
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
AC CHARACTERISTICS(TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.)
TEST CONDITIONS
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads
* The above test conditions are also applied at industrial temperature range.
For Cisco CMOS SRAM
Value 0V to 3V 3ns 1.5V See below
Output Loads(A) +5V 480 DOUT 255 30pF*
Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V 480 DOUT 255 5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD K6E0808C1E-10 Min 10 3 0 0 0 3 0 Max 10 10 5 5 5 10 K6E0808C1E-12 Min 12 3 0 0 0 3 0 Max 12 12 6 6 6 12 K6E0808C1E-15 Min 15 3 0 0 0 3 0 Max 15 15 7 7 7 15 Unit ns ns ns ns ns ns ns ns ns ns ns
* The above parameters are also guaranteed at industrial temperature range.
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Revision 2.0 Feburary 1999
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
WRITE CYCLE*
Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW K6E0808C1E-10 Min 10 8 0 8 8 10 0 0 5 0 0 Max 5 K6E0808C1E-12 Min 12 9 0 9 9 12 0 0 6 0 0 Max 6 -
For Cisco CMOS SRAM
K6E0808C1E-15 Min 15 10 0 10 10 15 0 0 7 0 0 Max 7 Unit ns ns ns ns ns ns ns ns ns ns ns
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC Address tAA Data Out Previous Valid Data Valid Data
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Revision 2.0 Feburary 1999
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
TIMING WAVEFORM OF READ CYCLE(2)
(WE=VIH)
For Cisco CMOS SRAM
tRC Address tAA tCO tOE OE tOLZ Data out VCC Current ICC ISB tLZ(4,5) Valid Data tPU 50% tPD 50% tOH tOHZ tHZ(3,4,5)
CS
NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5)
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Revision 2.0 Feburary 1999
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
For Cisco CMOS SRAM
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW
(10) (9)
tWR(5)
tWP1(2)
tDH
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in tDH tWP(2) tWR(5)
High-Z
tLZ tWHZ(6)
Valid Data
High-Z
Data out
High-Z
NOTES(WRITE CYCLE)
High-Z(8)
1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
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Revision 2.0 Feburary 1999
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
FUNCTIONAL DESCRIPTION
CS H L L L
* X means Dont Care.
For Cisco CMOS SRAM
I/O Pin High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC ICC
WE X H H L
OE X* H L X
Mode Not Select Output Disable Read Write
DATA RETENTION CHARACTERISTICS*(TA=0 to 70C)
Parameter VCC for Data Retention Data Retention Current Data Retention Set-Up Time Recovery Time Symbol VDR IDR tSDR tRDR Test Condition CSVCC-0.2V VCC=3.0V, CSVCC-0.2V VINVCC-0.2V or VIN0.2V See Data Retention Wave form(below) Min. 2.0 0 5 Typ. Max. 5.5 0.5 Unit V mA ns ms
* The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-Ver only.
DATA RETENTION WAVE FORM
CS controlled
VCC 4.5V tSDR Data Retention Mode
tRDR
VIH VDR CSVCC - 0.2V
CS GND
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Revision 2.0 Feburary 1999
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
PACKAGE DIMENSIONS
28-SOJ-300
#28 #15
For Cisco CMOS SRAM
Units:millimeters/Inches
7.62 0.300
8.51 0.12 0.335 0.005
6.86 0.25 0.270 0.010
0.20 #1 18.82 MAX 0.741 18.41 0.12 0.725 0.005 ( ( 1.30 ) 0.051 0.051 ) #14 0.69 MIN 0.027
+0.10 -0.05
0.008+0.004 -0.002
3.76 MAX 0.148
0.10 0.004 MAX
(
0.95 ) 0.0375
0.43
+0.10 -0.05
0.017 +0.004 -0.002
1.27 0.050
0.71
+0.10 -0.05
0.028+0.004 -0.002
28-TSOP1-0813.4F
0.10 MAX 0.004 MAX
+0.10 -0.05 +0.004 0.008 -0.002
0.20
13.40 0.20 0.528 0.008 #28 ( 0.425 ) 0.017
#1
8.40 0.331 MAX 0.55 0.0217 #14 #15 0.25 0.010 TYP 11.80 0.10 0.465 0.004
1.00 0.10 0.039 0.004 0.15 0.006
+0.10 -0.05 +0.004 -0.002
8.00 0.315
1.20 0.047 MAX
0.05 0.002 MIN
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
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Revision 2.0 Feburary 1999

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